The use of phase shift encoding for digital data is widely known. Apparatus and methods for quadri-phase shift key (QPSK) encoding and decoding of information typically provide a phase modulation carrier, having a phase shift with respect to the unmodulated carrier of 0.degree., 90.degree., 180.degree. or 270.degree..
In differential QPSK systems it is known to encode the information by the differential phase shift between baud intervals, rather than by the absolute magnitude of phase shift provided for the carrier during each baud interval.
Prior art approaches to demodulation of a received differential QPSK system signal are complex, and require extensive, expensive arithmetic and logic circuitry for decoding of the received signals. Additionally, where synchronous demodulation is provided, a carrier signal is generated within the receiving circuitry. The carrier signal must be kept at an appropriate phase with respect to the received signals. Error correction circuitry for correction of any phase errors in the internally generated carrier requires complex circuitry having a large component count.
Accordingly, there is a need in the prior art for simplified circuits for use in a synchronous demodulator for phase shift keyed signals.
There is, more specifically, a need for simplified digital circuitry to perform decoding of the received signals and further to provide phase correction for an internally generated carrier.
One digital detection system for differential phase shift keyed signals is disclosed in Gilmore et al. U.S. Pat. No. 3,993,956, wherein analog operations are performed on a received modulated analog signal to decode the digital information contained therein.
The disclosed circuit is quite complex for realization in integrated circuitry, requiring the use of complex matched filter circuits, for example.
A digital demodulator system is described in Nahay et al. U.S. Pat. No. 3,514,702, in which a number of separate counters are used to provide bit decision and phase coherency with the incoming signal transitions.
Another digital demodulator circuit is disclosed in Hawkeye et al. U.S. Pat. No. 3,728,484, similarly requiring complex circuitry together with a plurality of counters.
There is thus a need in the prior art for simplified circuitry capable of demodulating incoming signals and assuring proper phasing of internally generated carriers, preferably utilizing the same circuitry for demodulating the signal and for correcting any phase errors in the reconstituted carrier.
It is accordingly a primary object of the present invention to provide a simplified digital circuit for use in systems for demodulating phase shift keyed signals.
Another object of the invention is the provision of a circuit for synchronous demodulation of a phase shift keyed carrier, in which a reconstructed carrier is corrected by signals generated in the demodulating circuit itself.
It is a more specific object of the invention to provide a synchronous demodulating circuit utilizing a counter both for reaching a decision on decoding a received carrier and for measuring phase differences between a reconstructed carrier internally generated and the transmitted carrier.
Still another object of the invention is the provision of a counter having a full count suitably selected with respect to the internal operating frequencies to provide a half count therein for decoded signal representing any of the four possible phase shifts in a received signal, when an internally reconstructed carrier is in proper phase relationship.
An additional object of the invention is the use of a rollover signal generated by a detecting counter for indicating a decoded value of a received signal, and further for using the time necessary to obtain a rollover signal to correct any error in the internally generated reconstructed carrier.